a. Field of the Invention
The present invention generally relates to clock signals, and more particularly to maintaining the integrity of phase relationships between clock signals.
b. Background of Invention
Clock signals may be used in, among other things, digital communications and digital systems in general. As the integrity of the clock signals deteriorate, so may the overall operation and/or performance of the system. Quadrature clocks may be used in many digital system applications such as high-speed digital transmitters and receivers. Quadrature clocks may typically include two clock signals having a phase separation or difference of 90° (π/2).
Clock skew problems may cause a departure in the 90° (π/2) phase relationship of quadrature clock signals, which in turn may impact the system performance of the device or system using these clock signals. For example, in high-speed communication applications where quadrature clock signals provide the requisite timing for signal transmission and reception, phase variations in quadrature clock signals may ultimately cause an increase in bit-error rate (BER).
Variations in process, voltage, and temperature (PVT) may contribute to causing clock skew within, for example, semiconductor devices that include quadrature clocks. In addition, unmatched clock paths within circuits may also contribute to increased clock skew problems. It may, therefore, be advantageous, among other things, to maintain requisite phase relationships between signals such as for example, quadrature clock signals.